Here’s what I know about x86 kernel development. The usual caveat applies for my lab notes: this is not considered a high quality document and there may be inaccuracies.

Main Processor Modes

• Real Mode (16 bit)
  • CPU boots into this mode for backward compatibility
  • The IDT is instead the IVT here (Interrupt Vector Table)
  • Legacy BIOS booting begins here — the BIOS loads the first sector of disk into memory at a fixed address and begins executing it in Real Mode.
• Protected Mode (32 bit)
  • Segmentation is mandatory — a minimal GDT is necessary.
  • Paging is not mandatory
• Long Mode (64 bit)
  • Paging is mandatory

Segmentation

• Originally solved the problem of CPUs having more physical memory than could be addressed with 16 bit registers. (Note, this is the opposite situation of what we have today where virtual address spaces are vastly greater than physical ones)
• Introduces the concept of “segments”, which are variable length “windows” into a larger address space.

Data structures

GDT (Global Descriptor Table)

• Contains “descriptors” to describe the memory segments (“windows”) available. Segment register contain effectively an index into this table.
• There are “normal” descriptors which describe memory segments and “system” descriptors which point to more exotic things, like Task State Segments (TSS) or Local Descriptor Tables (LDT)
• These days OSs use the GDT as little as possible, only as much as strictly necessary. On 32 bit, this looks like 4 entries that start at base 0x0, and cover the entire 32 bit space. 2 for kernel, 2 for user — 1 for code, 1 for data for each. (?)
• On 64 bit GDT is totally unused (I believe?), as are nearly all segment registers(?), except FS and GS. (Why are they special? There is even a special MSR for GS?)

LDT (Local Descriptor Table)

• My understanding is LDTs are really no longer used by nearly any OS. Some parts of segmentation are still required by OSs, like the GDT, but LDT is not required and almost completely unused in modern OSs.
• These would contain segments only accessible to a single task, unlike the regions in the GDT (?)

IDT (Interrupt Descriptor Table)

• Interrupts: Generally externally triggered, i.e. from hardware devices
• Exceptions: Internally generated, I.e. division by zero exception, or software breakpoint
• When the processor receives an interrupt or exception, it handles that by executing code — interrupt handler routines.
• These routines are registered via the IDT — an array of descriptors that describes how to handle a particular interrupt.
• Interrupts/exceptions have numbers which directly map to entries in the IDT.
• IDT descriptors are a polymorphic structure — there are several kinds of entities: interrupt, trap, and task gates (maybe others – call gates?).
• Interrupt/trap gates are nearly identical and differ only in their handling of the interrupt flag. They contain a pointer to code to execute. This is expressed via a segment/offset.
• Task gates make use of HW task switching and offer a more “turnkey” solution for running code in a separate context when an interrupt happens — but generally aren’t used for other reasons (?). Context switch is automatic?
• Task gates in the IDT point to a TSS descriptor in the GDT, which points to a TSS (?)
• Some interrupt/exceptions have an associated error code, some don’t.
• Interrupt gates describe a minimal privilege level required to trigger then with an int instruction — this prevents userspace from triggering arbitrary interrupts with int. If userspace tries to trigger an int without permission, that is converted in to a General Protection fault (#GP)

Hardware task switching

• Although long considered obsolete in favor of software task/context switching, x86 provides significant facilities for modeling OS “tasks” at the hardware level, and including functionality for automatic context switching between them.
• Hardware task switching may require copying much more machine state than is necessary. Software context switches can be optimized to copy less and be faster, which is one reason why they’re preferred.
• Hardware task switching puts a fixed limit on the number of tasks in the system (?)

TSS (Task State Segment)

• This is a large structure modeling a “task” (thread of execution)
• Contains space for registers & execution context
• Even if HW task switching is not used, one TSS is still needed as the single HW Task running on the system, which internally implements all software context switching
• TSS is minimally used for stack switches when handling interrupts across privilege levels — when switching from userspace to kernel during interrupt, kernel stack is taken from TSS
• Linux task_struct is probably named with “task” due to being original created for i386
• The Task Register (TR) contains a descriptor pointing to the current active HW task (?)

The JOS boot process

JOS is the OS used in MIT 6.828 (2018).

Bootloader

• JOS includes a small BIOS bootloader in addition to the kernel
• The bootloader begins with typical 16 bit Real Mode assembly to do the typical steps to initialize the CPU (Set A20 line, etc)
• Transition to protected mode
• Set the stack immediately at the start of the code, and transition to C
• The kernel is loaded from disk using Port IO
• Loaded into physical memory around the 1MB mark, which is generally considered a “safe” area to load into. (Below the 1MB mark has various regions where devices, BIOS data, or other “things” reside and it’s best to not clobber them.)
• Call into the kernel entrypoint

Early kernel boot

• Receive control from the bootloader in protected mode
• Transition to paging
• The kernel is linked to run in high memory, starting at 0xf000000 (KERNBASE)
• The transition from segmentation to paging virtual memory happens in a few steps. There’s first an initial basic transition using set of minimal page tables.
• After that transition is made, a basic memory allocator is set up, which is then used to allocate memory for the production page tables which implement the production virtual memory layout used for the rest of runtime.
• The minimal page tables contain two mappings:
  • 1 – Identity map the first 4MB to itself
  • 2 – Map the 4MB region starting at KERNBASE also to the first 4MB
• One page directory entry maps a 4MB region, so only two page directory entries are needed
• These page tables are constructed statically at compile time
• The first identity mapping is critical because without it the kernel would crash immediate after loading CR3, because the next instruction would be unmapped. The identity mapping allows the low mem addresses the kernel resides in to remain valid until the kernel can jump to high mem
• The assembly there looks a bit strange because the jump appears redundant. But all the asm labels are linked using highmem addresses, so jumping to them transitions from executing in low mem, to executing in high mem, where the kernel will remain executing for the rest of its lifetime.
• Set the stack pointer to a global data/BSS section of internal storage within the kernel and enter C code

Memory allocators

• The goal is transition to a production virtual memory setup
• This requires allocating memory for page tables
• To build the dynamic page/frame allocator, we start with a basic bump allocator
• It starts allocating simply from the end of the kernel in memory. We have access to a symbol for the end of the kernel via a linker script.
• Kernel queries the physical memory size of the system and dynamically allocates data structures for the dynamic page/frame allocator. This is an array of structure that correspond to each available frame of physical memory. These structures have an embedded linked list pointer (intrusive linked list) and a refcount. They are linked together into a linked list, to implement a stack data structure where frames can be popped (when allocating) and pushed (when freeing).
• Using this frame allocator, pages for the production page tables are allocated.